The present invention relates generally to memory devices, and more particularly to a memory array architecture for multi-data rate operation.
Memory devices are integral to a computer system, and to many electronic circuits. Constant improvements in the operating speed and computing power of a central processing unit (CPU) enables operation of an ever-greater variety of applications, many of which require faster and larger memories. Larger memories can be obtained by shrinking the geometry of the memory cells and data lines within memory devices. However, with regard to memory speed, the access time for a memory device is generally governed by certain limitations. More particularly, memory speed is, to a large extent, dictated by the charge and discharge rates of parasitic capacitance on memory data lines.
Conventionally, a memory access to retrieve a data bit is performed by: (1) activating a row control line (e.g., a row select line or a word line) for the data bit; (2) waiting for the charge that is stored in a memory cell corresponding to the data bit to generate a voltage on a sense line; (3) sensing the charged voltage on the sense line to determine the value of the data bit; (4) activating a column select line; and (5) providing the detected bit value to a data line. A memory access to write a data bit is performed by: (1) activating the row control line for the required memory location; (2) receiving a write command and the associated data bit; (3) activating the column select line; and (4) providing the data bit to the memory cell. Conventionally, the steps for a memory read or a memory write are performed in sequential order for each accessed data bit.
The processes described above typically define the access time of a memory device (i.e., to retrieve or to write a data bit). The access time determines the maximum data transfer rate to or from a memory device. Traditionally, improvement in the access time of a memory read is limited to the time it takes to charge the sense line. Incremental improvements can be made to decrease the charge time by reducing the geometry of the device, thereby reducing the parasitic effects.
Large improvement in the data retrieval rate can be achieved by performing a concurrent prefetch of two data bits from memory and providing the retrieved bits on two data lines. In this manner, the memory device operates in a double-data-rate (DDR) operation. Large improvement in the data write rate can be achieved in a similar manner by (serially) receiving two data bits, aligning the data bits, and performing a concurrent double write to memory.
Conventionally, a concurrent read or write of two data bits requires additional circuitry, such as more internal data lines and sense amplifiers. The additional circuitry, while increasing the data transfer rate, results in larger die area and increased circuit cost. The increased die area is essentially a "die penalty" for the ability to concurrently access two data bits.